1. Field of the Invention
The present invention relates to electronic imaging. More particularly, the present invention is related to the structural design of a wafer-scale linear image sensor chip and method of making.
2. Related Background Art
An important trend of electronic imaging with a linear image sensor chip is the increase of total imaging length while preserving high pixel-pixel registration accuracy within the chip, ideally absent of any anomalous inter-pixel gaps. Other than a fundamental limitation imposed upon the total imaging length by the semiconductor wafer size, another potential indirect limitation on the total imaging length comes from a maximum allowable imaging field size (MIFS) of a wafer processing foundry fabricating the semiconductor wafer and this is illustrated in FIG. 6 and FIG. 7. More specifically, the MIFS is the maximum allowable single imaging field size of a precision step-and-repeat photolithographic imaging equipment defining the specific integrated circuit pattern to be created out of the wafer. Here, a specific MIFS is characterized by a maximum allowable imaging field size MIFSX along the X-direction and a maximum allowable imaging field size MIFSY along the Y-direction.
To keep the illustration free from the fundamental limitation imposed by the wafer size, two linear image sensor chips (LISC) 10 and LISC 20, both sized the same with a sensor chip length SCL and sensor chip width SCW smaller than the wafer size, are respectively shown in FIG. 6 and FIG. 7. A maximum allowable imaging field 8, of size MIFSX and MIFSY, are superimposed upon the sensor chip images. While SCW is smaller than MIFSY, SCL exceeds MIFSX and the circuit design of both LISC 10 and LISC 20 need to be partitioned into a number of sensor segments each sized within the maximum allowable imaging field 8 to allow photolithographic imaging through mask set(s) in a step-and-repeat manner. Thus, LISC 10 is partitioned into sensor segment SS1 10a, sensor segment SS2 10b, sensor segment SS3 10c and sensor segment SS4 10d. Similarly, LISC 20 is partitioned into sensor segment SS1 20a, sensor segment SS2 20b, sensor segment SS3 20c and sensor segment SS4 20d. 
Turning now to the key difference between LISC 10 and LISC 20. The circuit design of LISC 10 is such that the four sensor segments SS1 10a-SS4 10d are identical whereas that of LISC 10 is such that the four sensor segments SS1 20a-SS4 20d are different although SS1 20a equals SS3 20c and SS2 20b equals SS4 20d. As a result, LISC 10 can be photolithographically imaged with a single first mask set 1 whereas LISC 20 must be photolithographically imaged with a far more complicated procedure, called wafer stitching technology, using two interleaved mask sets 1 and 2 with corresponding switching of mask sets inserted in an otherwise much simpler step-and-repeat process. Consequently, while the wafer stitching technology can achieve long sensor chip size exceeding the MIFS with total flexibility of circuit design, its usage of multiple mask sets substantially lowers the photolithographic imaging throughput thus causes the sensor chip to be very high cost. Furthermore, the fact that each modern day mask set itself actually includes in the neighborhood of 10˜20 photo masks vastly exacerbates this throughput problem. As an example feedback from a wafer foundry, the production throughput per wafer under wafer stitching technology using two (2) mask sets is about six (6) times slower than an otherwise single mask set process.
FIG. 8 illustrates another prior art technology called chip-chip butting with a superimposed maximum allowable imaging field 8 of size MIFSX and MIFSY. Instead of “stitching” sensor elements at the wafer level, individual image sensors chip-1 34a through chip-7 34g, each previously diced off from a wafer with size smaller than the maximum allowable imaging field 8, are pairwise butted against each other and affixed onto a butting substrate 32 to form a final butted linear image sensor 30. While chip-chip butting totally avoids the problem of low wafer imaging throughput associated with the aforementioned wafer stitching technology, the totally mechanical nature of chip-chip butting usually leaves an undesirable butting gap between neighboring chips. This is illustrated with a butting gap BTGP of 10˜20 micron between image sensor chip-3 34c and image sensor chip-4 34d. Clearly these butting gaps cause a loss of pixel-pixel registration accuracy within the butted linear image sensor 30. Accordingly, it is a primary object of the present invention to provide a long linear image sensor chip exceeding the MIFS with absence of any anomalous inter-pixel gaps while avoiding the problem of low wafer imaging throughput associated with wafer stitching technology.